Agentic AI Use cases

Late changes, obsolete parts and verification decide when a product ships.

Idea-to-Market runs from the roadmap decision to production release: requirements, design and verification, tapeout, qualification, ramp and launch.

IDEA-TO-MARKET · FIVE PHASES · 194 DESIGNED ROLES, YET TO BE BUILT01Conceive42 roles · roadmap,requirements,architecture02Design60 roles · RTL,verification, physicaldesign03Tapeout and silicon34 roles · masks,foundry, bring-up04Qualify25 roles · reliability,safety, test05Launch33 roles · ramp,documents, lifecycleTHE FOUR THE MARKET IS DEPLOYING NOW, AND THE REST OF THE MAPRegression triageand debug closureDesign · 8 roles · A3Engineering changeimpactConceive to Launch · 7roles · A2Componentend-of-life watchLaunch and Design · 7roles · A2Launch readinesschecksLaunch and Qualify · 14roles · A3163 more rolesadditional capability
Five phases of the chain from the agent blueprint, with the number of designed roles in each, and the four use cases the market is deploying now beneath them. Every role is designed and yet to be built.
60% to 70%
of a chip project’s engineering effort goes to verification (Siemens, 3 September 2025)
dated source
14%
first-silicon success in the 2024 Wilson Research Group study, with 75% of projects late (Semiconductor Engineering, 27 March 2025)
dated source
7.0 days
median engineering change order, from request to production, across 4,075 companies (APQC, checked 23 September 2026)
dated source
620,000+
electronic parts discontinued in 2025; 52% reached end-of-life before a change notice (Z2Data, 13 March 2026)
dated source
The chain in the market

Where the time and the money go

Idea-to-Market runs from the roadmap decision to production release: requirements, architecture, design and verification, tapeout, bring-up, qualification, test at an OSAT (the outsourced assembly and test partner), ramp and launch. Tapeout is the moment the finished design goes to the foundry to make masks. The money goes to three places. Engineering effort first: verification alone takes 60% to 70% of a chip project’s effort (Siemens, 3 September 2025) 32. Respins and slips second; a respin is a second pass through the foundry to fix the design. First-silicon success fell to 14% in the 2024 Wilson Research Group study, 75% of projects ran late and 70% of respins traced to specification changes (Semiconductor Engineering, 27 March 2025) 31.

Change is the third. An engineering change order, an ECO, is the record that alters a design, its bill of materials (BOM) and everything built from it. The median ECO takes 7.0 days from request to production, and change orders take a median 10% of new product development cost (APQC, checked 23 September 2026) 28, 29; 90% of engineering leaders delay launches because of late design changes (CoLab, 26 July 2024) 30. Obsolescence is a constant drag: over 620,000 electronic parts were discontinued in 2025, and 52% reached end-of-life before a change notice was issued (Z2Data, 13 March 2026) 22. One redesign to resolve an obsolete part averaged $1.09 million (US Department of Commerce BIS, 2015) 25.

Agents are arriving fastest inside the design tools, where Synopsys, Cadence and Siemens ship named agents with customer numbers in 2026 33, 37, 41. They come next in the product lifecycle management (PLM) and ERP systems, where Siemens, SAP, Oracle, PTC, Aras and Dassault Systèmes ship change, replacement and readiness agents 1, 3, 6, 10, 16, 20. Analyst coverage is thin. Gartner’s 2026 report on PLM software expects agent-driven cross-functional workflows, as quoted by two vendors (PTC Arena, 11 August 2026; Siemens, 10 June 2026) 18, 57. Capgemini finds over 75% of engineering executives expecting 20% to 50% gains (Capgemini Research Institute, 13 November 2025) 47. Analyst surveys have yet to rank agent use cases inside product development, so this page leans on vendor offers, named customers and measured pain.

Deploying now

The use cases companies are deploying now

The research note ranked fifteen candidates on four criteria, in order of weight: adoption evidence, vendor offer density, named customer results and measured pain. A candidate entered the top four only where the blueprint holds a role for it. Regression triage scored highest on every criterion 33, 37, 41. Specification-to-RTL generation scored second and stays out: it belongs to the design tools, and the blueprint has yet to carry a role for it. Engineering change impact, component end-of-life and launch readiness follow on named agents from six PLM and ERP vendors and on measured pain 1, 3, 6, 22, 28, 30; launch readiness beat requirements traceability on adoption evidence after a tie on points. Engineering data search, the PLM assistant, is the Ask stage every use case includes, so it is treated as a feature.

Each page works the use case through the six stages, names who does what at which level, and lists the settings you would make.

Additional capability

The rest of the map for this chain

Lima’s agent blueprint is a design of 960 agent roles across five end-to-end chains. It is the map of what Juno can be configured to do, and the first agents are built from it one at a time, the way the PO cancellation agent was.

Everything below is designed and yet to be built. Each role is configured from the same parts as the use cases above, and a role that matters to you can be the next agent built.

Blueprint · designed, yet to be builtEach role can be configured from the same parts as the worked use cases: an objective, a data scope, rules, a trigger, actions, limits, an escalation route and a level.
Conceive · Portfolio & roadmap planning 9 roles
Market & TAM signal aggregation A3Roadmap scenario modelling A1Competitive silicon benchmarking A3Portfolio prioritisation & ranking A1Roadmap commit decision A0Node & platform selection A0Derivative & SKU planning A2Roadmap-to-capacity alignment A2Programme portfolio health report A3
Conceive · Requirements & market definition 6 roles
Customer requirement capture A2Requirement traceability matrix A3Spec conflict & gap detection A3Lead-customer co-definition A0Compliance & standards mapping A2Foundry customer PDK needs A2
Conceive · Programme funding & governance 7 roles
Business case & NPV modelling A1Funding gate decision A0Schedule & milestone planning A2Risk register & mitigation A3Cross-programme dependency map A3Programme cost & spend tracking A3Gate review pack assembly A3
Conceive · Architecture & IP planning 9 roles
Architecture exploration & model A1Performance & power budgeting A2IP reuse & catalogue matching A3Make-vs-license IP decision A0Chiplet & partitioning strategy A1Interface & protocol compliance A2Die size & floorplan estimation A2Architecture spec generation A2Architecture review evidence A3
Conceive · Software & firmware co-planning 8 roles
Driver & SDK scope definition A2Firmware architecture alignment A2HW-SW interface spec control A3Toolchain & compiler readiness A3Software milestone sync to silicon A3Reference stack & OS support plan A2Software IP & licence compliance A2Software release train planning A3
Design · RTL design & functional verification 4 roles
RTL lint & style compliance A4Testbench & stimulus generation A2Formal property setup & proof A2Emulation & prototype workloads A3
Design · Design-for-test & DFT insertion 8 roles
Scan insertion & compression A2ATPG generation & coverage A3MBIST / LBIST architecture A2Boundary scan & JTAG compliance A3DFT-to-ATE pattern handoff A3Diagnosis & failure mapping A3Test-mode power & timing check A3DFT coverage signoff A2
Design · Physical design & signoff 9 roles
Synthesis & constraint management A3Place-and-route iteration control A3Timing closure analytics A3Power, IR-drop & EM analysis A3DRC / LVS violation triage A3Signal & thermal integrity checks A3DFM & yield-aware optimisation A2Signoff checklist & waiver control A2Tapeout signoff authorisation A0
Design · Analog / mixed-signal & custom design 8 roles
Analog block spec & budgeting A2Schematic & layout co-design A2Monte Carlo & corner simulation A3Mismatch & variation analysis A3SerDes & high-speed IO closure A2PLL, LDO & bandgap validation A2AMS verification & co-simulation A3Custom layout DRC & matching A3
Design · IP, EDA & third-party management 8 roles
IP licence & entitlement tracking A3Third-party IP qualification A2IP version & bill-of-IP control A3Foundry IP ecosystem alignment A2Open-source & licence compliance A2Vendor escalation & support A3IP security & provenance audit A2IP integration readiness check A3
Design · Design infrastructure & compute 6 roles
EDA licence utilisation optimisation A3Cloud burst & cost control A3Environment & tool version control A3Design-team access & IP firewall A2Compute cost-per-tapeout analytics A3Infrastructure incident response A2
Design · Design data & configuration control 6 roles
Design data management & revision A3Release & branch control A3Bill-of-IP configuration A3Design handoff package control A3Golden-reference integrity A3Archive & reproducibility A4
Tapeout and Silicon · Tapeout & mask preparation 7 roles
GDS assembly & final integration A2Mask data prep & OPC handoff A2Reticle set planning & ordering A3Tapeout package completeness A4Shuttle / MPW slot booking A3Mask cost & write-time tracking A3Tapeout schedule risk monitoring A3
Tapeout and Silicon · Process, PDK & foundry interface 9 roles
PDK version & update management A3Process option & recipe selection A2Internal vs external foundry choice A0Foundry technical query handling A2Design rule waiver negotiation A1Foundry customer enablement pack A2Process qualification tracking A3Cross-foundry portability analysis A2IP-firewall control on design data A2
Tapeout and Silicon · Silicon bring-up & debug 9 roles
First-silicon test plan generation A2Bring-up result ingest & triage A3Failure isolation & FA coordination A2Silicon-vs-model correlation A3Speed path & shmoo analysis A3Errata capture & disclosure control A2Metal / base layer respin decision A0Bring-up status reporting A3Debug knowledge base curation A3
Tapeout and Silicon · Post-silicon validation & software bring-up 8 roles
System-level validation planning A2Driver & firmware bring-up A2Compliance & interop testing A2Application workload benchmarking A3Thermal & power characterisation A3Validation coverage tracking A3Errata-to-software workaround A2Customer platform validation A2
Qualify · Product & reliability qualification 6 roles
Qualification plan generation A2Reliability stress monitoring (HTOL) A3Qual data collection & analysis A3Package & board-level qual A2Qual exception & waiver review A1Qualification report assembly A3
Qualify · Automotive, safety & standards certification 8 roles
Automotive & safety qualification A2ISO 26262 work-product assembly A2FMEDA & diagnostic coverage A2AEC-Q100 grade compliance A2Standards & regulatory certification A2Cybersecurity (ISO 21434) evidence A2Certification body liaison A1Safety case sign-off A0
Qualify · Test & product engineering 7 roles
Test coverage & DPPM modelling A3Yield ramp analytics & learning A3Bin definition & speed grading A2Test time & cost reduction A3Characterisation & datasheet limits A2Outlier screening rule tuning A3Production test correlation A3
Launch · NPI ramp & supply readiness 2 roles
Yield learning curve tracking A3Cost-per-unit ramp modelling A3
Launch · Launch documentation & collateral 6 roles
Datasheet & document generation A2Errata & app-note publication A3Document version & release control A3Regulatory & compliance labelling A2Translation & localisation A3Document accuracy review A1
Launch · Sales, FAE & ecosystem enablement 7 roles
Pricing & positioning input A1Reference design & kit release A2Sales & FAE enablement pack A3Customer sampling & eval logistics A3Design-in support content A3Ecosystem & partner enablement A2Training & certification material A3
Launch · Post-launch quality & lifecycle watch 6 roles
Post-launch quality & field watch A3Early field-return analytics A3Design-win to revenue tracking A3Customer satisfaction signal A3Yield & cost maturity tracking A3Launch retrospective & learning A2
Measured

How the chain is measured

MeasureWhat it shows
Time to RTL freezeHow long verification takes to reach the gate after which the design code changes only by change order, against the plan
First-silicon successWhether the first silicon works; baseline 14% in the 2024 Wilson Research Group study (Semiconductor Engineering, 27 March 2025)
Change order cycle timeRequest to production implementation; baseline a median 7.0 days across 4,075 companies (APQC, checked 23 September 2026)
Change order cost shareChange orders as a share of new product development cost; baseline a median 10% across 325 companies (APQC, checked 23 September 2026)
Notices caught before end-of-lifeParts with a notice on record before the last order date; baseline 52% reached end-of-life before a notice (Z2Data, 13 March 2026)
Launches on timeShare of launches released on the planned date; baseline 10% of companies launch every product on time (CoLab, 26 July 2024)
Expedite spend during rampWhat it costs to recover a gap found at the first production order, in currency per launch
Next chain
The question this leaves

The product is released and its first orders arrive from the customers who evaluated samples. How does the same machinery carry an order from intake to cash?

Answered next

Order-to-Cash

Order intake, cash application, collections and disputes: the chain where the market’s evidence is deepest, and where the A0 and A4 scenes of the gamut live.

Sources

Dated sources used on this page

  1. [1] Siemens Digital Industries Software (Teamcenter blog), How AI BOM agents transform engineering change workflows, 23 June 2026 (checked 23 September 2026) · https://blogs.sw.siemens.com/teamcenter/ai-bom-agent-plm-engineering-change/
  2. [3] SAP News Center, Innovative Updates for Supply Chain Management (SAP Connect), 7 October 2025 (checked 23 September 2026) · https://news.sap.com/2025/10/sap-connect-innovative-updates-supply-chain-management/
  3. [6] Oracle Help Center, Oracle Fusion Cloud Product Lifecycle Management 26A What's New: Improved Component Replacement Assistant, 30 July 2026 (checked 23 September 2026) · https://docs.oracle.com/en/cloud/saas/readiness/scm/26a/plm26a/26A-plm-wn-f42907.htm
  4. [10] PTC, PTC Launches Arena AI Engine to Accelerate Intelligent Automation Across PLM and QMS Workflows, 9 December 2025 (checked 23 September 2026) · https://www.ptc.com/en/news/2025/ptc-launches-arena-ai-engine
  5. [16] Aras, Introducing the First Generation of Agents Built on Aras InnovatorEdge, 26 February 2026 (checked 23 September 2026) · https://aras.com/en/blog/introducing-the-first-generation-of-agents-built-on-aras-innovator-edge-ai
  6. [18] PTC Arena (blog quoting the Gartner Magic Quadrant for PLM Software in Discrete Manufacturing Industries, 9 June 2026), PTC (Arena) Named a Visionary in the 2026 Gartner Magic Quadrant for PLM in Discrete Manufacturing Industries, 11 August 2026 (checked 23 September 2026) · https://www.arenasolutions.com/blog/arena-2026-gartner-magic-quadrant-plm-visionary/
  7. [20] Dassault Systèmes, Dassault Systèmes Unveils a New Way of Working for Industry with AI-Powered Virtual Companions, 11 February 2026 (checked 23 September 2026) · https://www.3ds.com/newsroom/press-releases/dassault-systemes-unveils-new-way-working-industry-ai-powered-virtual-companions
  8. [22] Z2Data, Components Are Going EOL Without Product Change Notifications at Alarming Rates, 13 March 2026 (checked 23 September 2026) · https://www.z2data.com/insights/components-are-going-eol-without-product-change-notifications-at-alarming-rates/
  9. [25] US Department of Commerce, Bureau of Industry and Security, DMSMS Cost Metrics Report (2014 survey, 28 organisations, 4,562 issues), 2015 (checked 23 September 2026) · https://www.bis.gov/media/documents/dmsms-cost-metrics-report-2015-final.pdf
  10. [28] APQC, Engineering change order (ECO) cycle time in days (Open Standards Benchmarking measure; median 7.0 days, n=4,075), undated, checked 23 September 2026 (checked 23 September 2026) · https://www.apqc.org/what-we-do/benchmarking/open-standards-benchmarking/measures/engineering-change-order-eco-cycle
  11. [29] APQC, Engineering change order (ECO) costs as a percentage of the total new product development cost (median 10.0%, n=325), undated, checked 23 September 2026 (checked 23 September 2026) · https://www.apqc.org/what-we-do/benchmarking/open-standards-benchmarking/measures/engineering-change-order-eco-costs
  12. [30] CoLab Software (survey of 250 engineering leaders by Global Surveyz), 90% of companies delay product launches, 26 July 2024 (checked 23 September 2026) · https://www.colabsoftware.com/research/90-of-companies-delay-product-launches
  13. [31] Semiconductor Engineering (reporting the 2024 Siemens EDA and Wilson Research Group Functional Verification Study), First-Time Silicon Success Plummets, 27 March 2025 (checked 23 September 2026) · https://semiengineering.com/first-time-silicon-success-plummets/
  14. [32] Siemens Digital Industries Software (Verification Horizons blog), Why First-Silicon Success Is Getting Harder for System Companies, 3 September 2025 (checked 23 September 2026) · https://blogs.sw.siemens.com/verificationhorizons/2025/09/03/why-first-silicon-success-is-getting-harder-for-system-companies/
  15. [33] Synopsys, Synopsys Advances Agentic AI Chip Design with AMD and Microsoft, 27 July 2026 (checked 23 September 2026) · https://news.synopsys.com/2026-07-27-Synopsys-Advances-Agentic-AI-Chip-Design-with-AMD-and-Microsoft
  16. [37] EE Times, Cadence Unveils ChipStack AI Agent for Agentic Chip Design and Verification, 10 February 2026 (checked 23 September 2026) · https://www.eetimes.com/cadence-unveils-chipstack-ai-agent-for-agentic-chip-design-and-verification/
  17. [41] Siemens, Accelerating IC design and verification with agentic AI (Questa One Agentic AI Toolkit), 27 February 2026 (checked 23 September 2026) · https://news.siemens.com/en-us/questa-one-agentic-ai-toolkit/
  18. [47] Capgemini Research Institute, Engineering and R&D Pulse 2026, 13 November 2025 (checked 23 September 2026) · https://www.capgemini.com/insights/research-library/engineering-research-development-pulse-2026/
  19. [57] Siemens, Siemens is a Leader in Gartner Magic Quadrant for PLM Software in Discrete Manufacturing Industries (report dated 9 June 2026), 10 June 2026 (checked 23 September 2026) · https://news.siemens.com/en-us/teamcenter-gartner-magic-quadrant-plm-2026/

See Juno answer and act on your own data

Bring two systems and one decision your planners make every week. In the first week we register the data, confirm the mapping with your team, answer your questions in ChatLima and run the first agent at the level you choose.